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rev. e a ad7664 * information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2004 analog devices, inc. all rights reserved. 16-bit, 570 ksps pulsar unipolar cmos adc functional block diagram switched cap dac 16 control logic and calibration circuitry clock ad7664 d[15:0] busy rd cs ser/ par ob/ 2c ognd ovdd dgnd dvdd avdd agnd ref refgnd in ingnd pd reset serial port parallel interface cnvst warp impulse features throughput: 570 ksps (warp mode) 500 ksps (normal mode) 444 ksps (impulse mode) inl: 2.5 lsb max ( 0.0038% of full scale) 16-bit resolution with no missing codes s/(n+d): 90 db typ @ 45 khz thd: ?00 db typ @ 45 khz analog input voltage range: 0 v to 2.5 v both ac and dc specifications no pipeline delay parallel and serial 5 v/3 v interface spi /qspi tm /microwire tm /dsp compatible single 5 v supply operation power dissipation 115 mw maximum, 21 w @ 100 sps power-down mode: 7 w max package: 48-lead quad flat pack (lqfp) 48-lead chip scale package (lfcsp) pin-to-pin compatible upgrade of the ad7660 applications data acquisition instrumentation digital signal processing spectrum analysis medical instruments battery-powered systems process control general description the ad7664 is a 16-bit, 570 ksps, charge redistribution sar, analog-to-digital converter that operates from a single 5 v power supply. the part contains a high speed 16-bit sampling adc, an internal conversion clock, error correction circuits, and both serial and parallel system interface ports. the ad7664 is hardware factory-calibrated and is comprehen sively tested to ensure such ac parameters as signal-to-noise ratio (snr) and total harmonic distortion ( thd), in addition to the more traditional dc parameters of gain, offset, and linearity. it features a very high sampling rate mode (warp), a fast mode (normal) for asynchronous conversion rate applications, and for low power applications, a reduced power m ode (impulse) where the power is scaled with the throughput. it is fabricated using analog devices?high performance, 0.6 micron cmos process, with correspondingly low cost and is available in a 48-lead lqfp and a tiny 48-lead lfcsp with operation specified from ?0 c to +85 c. product highlights 1. fast throughput the ad7664 is a 570 ksps, charge redistribution, 16-bit sar adc with internal error correction circuitry. 2. superior inl the ad7664 has a maximum integral nonlinearity of 2.5 lsbs with no missing 16-bit code. 3. single-supply operation the ad7664 operates from a single 5 v supply and dissipates only a maximum of 115 mw. in impulse mode, its power dissi pation decreases with the throughput to, for instance, only 21 w at a 100 sps throughput. it consumes 7 w maximum when in power-down. 4. serial or parallel interface versatile parallel or 2-wire serial interface arrangement com patible with both 3 v or 5 v logic. table i. pulsar selection type/ksps 100?50 500?70 800?000 pseudo ad7651 ad7650/ad7652 ad7653 differential ad7660/ad7661 ad7664/ad7666 ad7667 true bipolar ad7663 ad7665 ad7671 true ad7675 ad7676 ad7677 differential 18-bit ad7678 AD7679 ad7674 simultaneous/ ad7654 multichannel ad7655
rev. e e2e ad7664 parameter conditions min typ max unit resolution 16 bits analog input voltage range v in e v ingnd 0v ref v operating input voltage v in e0.1 +3 v v ingnd e0.1 +0.5 v analog input cmrr f in = 10 khz 62 db input current 570 ksps throughput 7 a input impedance see analog input section throughput speed complete cycle in warp mode 1.75 s throughput rate in warp mode 1 570 ksps time between conversions in warp mode 1 ms complete cycle in normal mode 2 s throughput rate in normal mode 0 500 ksps complete cycle in impulse mode 2.25 s throughput rate in impulse mode 0 444 ksps dc accuracy integral linearity error e2.5 +2.5 lsb 1 differential linearity error e1 +1.5 lsb no missing codes 16 bits transition noise 0.7 lsb full-scale error 2 ref = 2.5 v 0.08 % of fsr unipolar zero error 2 5 15 lsb power supply sensitivity avdd = 5 v 5% 3 lsb ac accuracy signal-to-noise f in = 100 khz 90 db 3 spurious-free dynamic range f in = 45 khz 100 db f in = 100 khz 100 db total harmonic distortion f in = 45 khz e100 db f in = 100 khz e100 db signal-to-(noise+distortion) f in = 45 khz 90 db f in = 100 khz 89 db e60 db input, f in = 100 khz 30 db e3 db input bandwidth 18 mhz sampling dynamics aperture delay 2ns aperture jitter 5 ps rms transient response full-scale step 250 ns reference external reference voltage range 2.3 2.5 avdd e 1.85 v external reference current drain 570 ksps throughput 115 a digital inputs logic levels v il e0.3 +0.8 v v ih 2. 0 ovdd + 0.3 v i il e1 +1 a i ih e1 +1 a digital outputs data format parallel or serial 16-bits pipeline delay conversion results available immediately after completed conversion v ol i sink = 1.6 ma 0.4 v v oh i source = e500 a ovdd e 0.6 v power supplies specified performance avdd 4.75 5 5.25 v dvdd 4.75 5 5.25 v ovdd 2.7 5.25 v operating current 4 500 ksps throughput avdd 15.5 ma dvdd 5 3.8 ma ovdd 5 100 a power dissipation 5 500 ksps throughput 4 115 mw 100 sps throughput 6 21 w in power-down mode 7 7 w especifications (e40 c to +85 c, avdd = dvdd = 5 v, ovdd = 2.7 v to 5.25 v, unless otherwise noted.)
rev. e e3e ad7664 parameter conditions min typ max unit temperature range 8 specified performance t min to t max e40 +85 c notes 1 lsb means least significant bit. with the 0 v to 2.5 v input range, one lsb is 38.15 v. 2 see definition of specifications section. these specifications do not include the error contribution from the external referenc e. 3 all specifications in db are referred to a full-scale input fs. tested with an input signal at 0.5 db below full-scale unless o therwise specified. 4 in normal mode. 5 tested in parallel reading mode. 6 in impulse mode. 7 with all digital inputs forced to ovdd or ognd, respect ively. 8 contact factory for extended temperature range. specifications subject to change without notice. timing specifications parameter symbol min typ max unit refer to figures 11 and 12 convert pulse width t 1 5ns time between conversions t 2 1.75/2/2.25 note 1 s (warp mode/normal mode/impulse mode) cnvst s hih d 2 s hih a 2 s r c ( n i a d 2 c s d c t 2 ( n i a t 2 rst p rr t irs and (p i cnvst data v d 2 ( n i data v s d a r data v 2 r t rr t irs and ( s i 2 cs snc v d cs i sc v d 2 cs sdt d cnvst snc d 222 ( n i snc a sc d i sc p i sc hih (invsc 2 i sc (invsc 2 sdt v s t 22 sdt v h t 2 sc snc d 2 cs hih snc hi 2 cs hih i sc hi 2 cs hih sdt hi 2 s hih s r c 2 22 ( n i cnvst snc a d 2 2 ( n i snc d s d rr t irs and 2 (s s i 2 sc s t sc a sdt d 2 sdin s t sdin h t sc p 2 sc hih sc ( c c avdd dvdd v vdd 2 v 2 v nts i 2 i s i snc sc sdt c i sc sc s
rev. e e4e ad7664 ordering guide temperature model range package description package option ad7664ast e40 c to +85 c quad flatpack (lqfp) st-48 ad7664astrl e40 c to +85 c quad flatpack (lqfp) st-48 ad7664acp e40 c to +85 c chip scale (lfcsp) cp-48 ad7664acprl e40 c to +85 c chip scale (lfcsp) cp-48 eval-ad7664cb 1 evaluation board eval-control-brd2 2 controller board notes 1 this board can be used as a standalone evaluation board or in conjunction with the eval-control-brd2 for evaluation/ demonstration purposes. 2 this board allows a pc to control and communicate with all analog devices evaluation boards ending in the cb designators. absolute maximum ratings 1 in 2 , ref, ingnd, refgnd to agnd . . . . . . . . . . . . . . . . . . . . . . . avdd + 0.3 v to agnd e 0.3 v ground voltage differences agnd, dgnd, ognd . . . . . . . . . . . . . . . . . . . . . . 0.3 v supply voltages avdd, dvdd, ovdd . . . . . . . . . . . . . . . . e0.3 v to +7 v avdd to dvdd, avdd to ovdd . . . . . . . . . . . . . . 7 v dvdd to ovdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v digital inputs except the databus d(7:4) . . . . . e0.3 v to dvdd + 3.0 v databus d(7:4) . . . . . . . . . . . . . . e0.3 v to ovdd + 3.0 v internal power dissipation 3 . . . . . . . . . . . . . . . . . . . . 700 mw internal power dissipation 4 . . . . . . . . . . . . . . . . . . . . . . 2.5 w junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c storage temperature range . . . . . . . . . . . . e65 c to +150 c lead temperature range (soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. 2 see analog input section. 3 specification is for the device in free air: 48-lead lqfp; ja = 91 c/w, jc = 30 c/w. 4 specification is for device in free air: 48-lead lfcsp; ja = 26 c/w. i oh 500 a 1.6ma i ol to output pin 1.4v c l 60pf * * in serial interface modes, the sync, sclk, and sdout timings are defined with a maximum load c l of 10pf; otherwise, the load is 60pf maximum. figure 1. load circuit for digital interface timing, sd out, sync, sclk outputs, c l = 10 pf 0.8v 2v 2v 0.8v 0.8v 2v t delay t delay figure 2. voltage reference levels for timing caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7664 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
rev. e ad7664 e5e pin function descriptions pin no. mnemonic type description 1 agnd p analog power ground pin. 2 avdd p input analog power pins. nominally 5 v. 3, 40e42, nc no connect. 44e48 4 dgnd di must be tied to the ground where dvdd is referred. 5ob/ 2c di s t c 2c hih s arp di s hih ips ips di s hih arp i sr par di sp s i p p hih s i data s p 2 d d p p d t sr par d di sr par p p d t int sr par hih s p t int sc t int hih z sc d di sr par p p d invsnc sr par hih s p snc i s snc hih hih snc d di sr par p p d invsc sr par hih s p sc i s pin cniratin 2 2 2 2 2 2 2 2 22 2 2 2 2 2 pin idntiir tp vi (n s and cnvst pd rst cs rd dnd and avdd nc dnd 2c arp ips nc n cnnct sr par d d d2 s d d d ad d d2 dt int dinvsnc dinvsc drdcsdin nd vdd dvdd dnd dsdt dsc dsnc drdrrr nc nc nc nc nc in nc nc nc innd rnd r
rev. e e6e ad7664 pin no. mnemonic type description 16 d7 di/o when ser/ par p p d rdcsdin sr par hih s p r t int t int hih rdcsdin adc sdt t sdin data sc t int rdcsdin r rdcsdin hih sdt rdcsdin sdt nd p i i d p vdd p i i d p n ( v v dvdd p d p n v 2 dnd p d p 2 d d sr par p p d sdt sr par hih s p z sc c t ad s t data 2c i s t int s dt sc i s t int hih i invsc sdt sc i invsc hih sdt sc 22 d di sr par p p d s c sr par hih s p t int t sdt invsc 2 d d sr par p p d snc sr par hih s p z (t int invsnc snc hih hih sdt invsnc hih snc sdt 2 d d sr par p p d rdrrr sr par hih t int hih s p i s rdrrr hih 22 d2 d 2 p p d t sr par 2 s d t hih hih t s dnd p t d rd di r d cs rd 2 cs di c s cs rd cs rst di r i hih ad c i dnd pd di pd i hih
rev. e ad7664 e7e pin no. mnemonic type description 35 cnvst di s c a cnvst i i (ips hih arp cnvst ( and p t a r ai r i v rnd ai r i a innd ai a i in ai p a i r v v r nts ai a i di d i di d d d p p dinitin spciicatins i n (in t 2 s p 2 s t d n (dn i adc s d i s t ( 2 s (22 v v2 v t t 2 s ( v v2 v z s d r (sdr t ( n (n n i s(nd enob s n d db =+ [] ? () 176 602 .. and is expressed in bits. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic co m ponents to the rms value of a full-scale input signal and is expressed in decibels. signal-to-noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. signal to (noise + distortion) ratio (s/[n+d]) s/(n+d) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for s/(n+d) is expressed in decibels. aperture delay aperture delay is a measure of the acquisition performance and is measured from the falling edge of the cnvst t r t ad r t adc
rev. e e8e ad7664 2.5 inl e lsb code 65536 1.5 0 e1.5 e2.5 49152 32768 16384 0 1.0 e0.5 e2.0 2.0 0.5 e1.0 tpc 1. integral nonlinearity vs. code 8000 7f86 counts code e hexa 7f87 7f8f 7f8e 7f8d 7f8c 7f8b 7f8a 7f89 7f88 7000 6000 5000 4000 3000 2000 1000 0 753 7288 7148 1173 10 0 0 12 0 0 tpc 2. histogram of 16,384 conversions of a dc input at the code transition positive inl (lsb) 140 00.51.01 .5 2.0 2.5 number of units 130 120 110 100 90 80 70 60 50 40 30 20 10 0 tpc 3. typical positive inl distribution (600 units) 1.50 dnl e lsb code 65536 1.00 0.25 e0.50 e1.00 49152 32768 16384 0 0.75 0 e0.75 1.25 0.50 e0.25 tpc 4. differential nonlinearity vs. code 10000 7fb3 counts code e hexa 7fb4 7fbb 7fba 7fb9 7fb8 7fb7 7fb6 7fb5 8000 6000 5000 4000 3000 2000 1000 0 3340 9008 3643 257 00 136 0 0 9000 7000 tpc 5. histogram of 16,384 conversions of a dc input at the code center negative inl (lsb) 180 e2.5 e2.0 e1.5 e1.0 e0.5 0.0 number of units 170 160 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 tpc 6. typical negative inl distribution (600 units) etypical performance characteristics
rev. e ad7664 e9e frequency (khz) 057 114 171 285 228 amplitude (db of full scale) 0 e20 e180 e40 e60 e80 e100 e120 e140 e160 8192 point fft f s = 570khz f in = 45.5322khz, e0.5db snr = 90.1db sinad = 89.4db thd = e97.1db sfdr = 97.5db tpc 7. fft plot 1 snr and s/[n+d] e db frequency e khz 100 10 90 80 75 70 100 85 1000 95 enob e bits 15.0 14.0 13.5 13.0 16.0 14.5 15.5 snr s/(n+d) enob tpc 8. snr, s/(n+d), and enob vs. frequency 1 thd, harmonic e db frequency e khz 100 10 e70 e80 e85 e90 e95 e100 e105 e110 e60 e75 1000 e65 sfdr thd sfdr e db 100 90 85 80 75 70 65 60 110 95 105 second harmonic third harmonic tpc 9. thd, harmonics, and sfdr vs. frequency 92 e60 snr (referred to full scale) e db input level e db 0 e20 e40 90 88 86 snr s/(n+d) e50 e30 e10 tpc 10. snr and s/(n+d) vs. input level (referred to full scale) 96 e55 snr and s/(n+d) e db temperature e c e35 125 105 85 65 45 25 5 e15 93 90 87 84 e96 e98 e100 e102 e104 thd e db thd snr tpc 11. snr, s/(n+d), thd vs. temperature ovdd, all modes dvdd, impulse avdd, impulse dvdd, warp/normal avdd, warp/normal 100k 0.1 operating currents e a sampling rate e sps 100k 1k 10 1 100 10k 1m 10k 1k 100 10 1 0.1 0.01 0.001 tpc 12. operating currents vs. sample rate
rev. e e10e ad7664 e10 e8 e6 e4 e2 0 2 4 6 8 10 e55 e35 e15 5 25 45 65 85 105 125 temperature ( c) zero error, full-scale error (lsb) full-scale error zero error tpc 13. zero error, full-scale error vs. temperature 50 0 t 12 delay e ns c l e pf 200 50 20 10 0 100 150 30 40 ovdd = 5v, 25 c ovdd = 5v, 85 c ovdd = 2.7v, 85 c ovdd = 2.7v, 25 c tpc 14. typical delay vs. load capacitance c l temperature e c power-down operating currents e na 0 20 e40 e15 10 35 60 85 40 60 80 100 10 30 50 70 90 dvdd e10 avdd ovdd tpc 15. power-down operating currents vs. temperature
rev. e ad7664 e11e circuit information t he ad7664 is a very fast, low power, single-supply, precise 16-bit analog-to-digital converter (adc). the ad7664 fea tures different modes to optimize performances according to the applications. in warp mode, the ad7664 is capable of converting 570,000 samples per second (570 ksps). the ad7664 provides the user with an on-chip track-and- hold, successive-approximation adc that does not exhibit any pipeline or latency, making it ideal for multiple multiplexed channel applications. the ad7664 can be operated from a single 5 v supply and interfaced to either 5 v or 3 v digital logic. it is housed in a 48-lead lqfp package or a 48-lead lfcsp package that saves space and allows flexible configurations as either a serial or parallel interface. the ad7664 is a pin-to-pin com- patible upgrade of the ad7660. converter operation the ad7664 is a successive-approximation analog-to-digital converter based on a charge redistribution dac. figure 3 shows the simplified schematic of the adc. the capacitive dac consists of an array of 16 binary weighted capacitors and an additional lsb capacitor. the comparator?s negative input is connected to a dummy capacitor of the same value as the capacitive dac array. during the acquisition phase, the common terminal of the array tied to the comparator?s positive input is connected to agnd via sw a . all independent switches are connected to the analog input in. thus, the capacitor array is used as a sampling capacitor and acquires the analog signal on the in input. similarly, the dummy capacitor acquires the analog signal on the ingnd input. when the cnvst s a s t rnd t in innd rnd r (v r 2 v r v r t s a adc s t ad n i t sps h i t ad s a cp s in r rnd s s 2c innd c c 2c c c c cntr ic sitchs cntr s tpt cd cnvst adc s s
rev. e e12e ad7664 the normal mode is the fastest mode (500 ksps) without any limitation on the time between conversions. this mode m akes the ad7664 ideal for asynchronous applications such as data acquisition systems, where both high accuracy and fast sample rate are required. the impulse mode, the lowest power dissipation mode, allows power saving between conversions. when operating at 100 sps, for example, it typically consumes only 21 w. this feature makes the ad7664 ideal for battery-powered applications. transfer functions using the ob/ 2c ad t s z v r v t ad t ii adc cd s ana inpt v r s v r s s v s s v r adc i t t ii c i i v d c h a s t d i c sr s 22 v sr 2 s 22 v s 2 v 2 v s 22 v sr s v sr v 2 2 nts t (v in v innd v r v rnd 2 t (v in v innd tpica cnnctin diara ad avdd and dnd dvdd vdd nd arp ips sr par cnvst s sdt sc rd cs rst pd in innd rnd c r 2v r r d cc ad ana inpt (v t 2v c pdsp sria prt diita spp (v r v ana spp (v dvdd c c 2c 2 nts th adr2 is rcndd ith c r 2 th ad2 is rcndd ith a cpnsatin capacitr c c tp craic np ptina ittr cnvst t c d
rev. e ad7664 e13e analog input figure 6 shows an equivalent circuit of the input structure of the ad7664. c2 r1 d1 d2 c1 in or ingnd agnd avdd figure 6. equivalent analog input circuit t he two diodes d1 and d2 provide esd protection for the analog inputs in and ingnd. care must be taken to ensure t hat the analog input signal never exceeds the supply rails by more th an 0.3 v. this will cause these diodes to become forward- biased and start conducting current. these diodes can handle a forward-biased current of 100 ma maximum. for instance, these conditions could eventually occur when the input buffer?s (u1) supplies are different from avdd. in such cases, an input buffer with a short circuit current limitation can be used to protect the part. this analog input structure allows the sampling of the differen- tial signal between in and ingnd. unlike other converters, the ingnd input is sampled at the same time as the in input. by using this differential input, small signals common to both inputs are rejected, as shown in figure 7, which represents the typical cmrr over frequency. for instance, by using ingnd to sense a remote signal ground, difference of ground potentials between the sensor and the local adc ground are eliminated. 70 1k cmrr e db frequency e hz 1m 50 30 0 100k 60 40 20 10 10k figure 7. analog input cmrr vs. frequency during the acquisition phase, the impedance of the analog input in can be modeled as a parallel combination of capacitor c1 and the network formed by the series connection of r1 and c2. capacitor c1 is primarily the pin capacitance. the resistor r1 is typically 140 and is a lumped component made up of some serial resistors and the on resistance of the switches. the capacitor c2 is typically 60 pf and is mainly the adc sampling capacitor. during the conversion phase, where the switches are opened, the input i mpedance is limited to c1. the r1, c2 makes a one-pole low- pass filter that reduces the undesirable aliasing effect and limits the n oise. when the source impedance of the driving circuit is low, the ad7664 can be driven directly. large source impedances will significantly affect the ac performances, especially the total harmonic distortion (thd). the maximum source impedance depends on the amount of thd that can be tolerated. the thd degrades in function of the source impedance and the maximum input frequency as shown in figure 8. 10 thd e db frequency e khz 100 e85 e90 e95 e100 e70 e80 1000 e75 r = 11 r = 100 r = 50 figure 8. thd vs. analog input frequency and source resistance driver amplifier choice although the ad7664 is easy to drive, the driver amplifier needs to meet at least the following requirements: ? the driver amplifier and the ad7664 analog input circuit must be able, together, to settle for a full-scale step of the capacitor array at a 16-bit level (0.0015%). in the amplifier?s data sheet, the settling at 0.1% to 0.01% is more commonly specified. it could significantly differ from the settling time at 16-bit level and it should, therefore, be verified prior to the driver selection. the tiny op amp ad8021, which combines ultralow noise and a high gain bandwidth, meets this settling time requirement even when used with high gain up to 13. ? the noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the snr and transition noise performance of the ad7664. the noise coming from the driver is filtered by the ad7664 analog input circuit one- pole low-pass filter made by r1 and c2 or the external filter, if any is used. the snr degradation due to the amplifier is: snr fne loss ?3db n = + () 20 28 784 2 2 log where: f ?3 db is the e3 db input bandwidth in mhz of the ad7664 (18 mhz) or the cutoff frequency of the input filter, if any used. n is the noise gain of the amplifier (1, if in buffer configuration). e n is the equivalent input noise voltage of the op amp in nv/
hz
rev. e e14e ad7664 for instance, in a driver like the ad8021, with an equivalent input noise of 2 nv/
hz snr t thd ad tpc 2 thd t ad2 t ad2 t np t ad22 t ad2 ( hz i 2 t ad v r i t ad 2 v t r ad r rnd t sr r rnd t adr2 ad t adr2 t ad2 ad ad c c s c v r avdd v t snr s v r v v avdd v t (2 2 d z t ad v p s t ad v avdd v dvdd vdd t vdd 2 v 2 v t (dvdd rc t ad a pr dissipatin vrss thrhpt t i i ad t ad i t ( dvdd dnd t int invsnc invsc rdcsdin vdd nd psrr inpt rnc hz psrr pr dissipatin sapin rat sps arpnra ips p d s r
rev. e ad7664 e15e conversion control figure 11 shows the detailed timing diagrams of the conversion process. the ad7664 is controlled by the signal cnvst pd t cnvst cs rd cnvst s d 2 acir cnvrt acir cnvrt c t i i i cnvst s ad cnvst ad i s a cnvst i ad i sps t n rst datas s cnvst 2 rst t a cnvst i cnvst ( snr cnvst t cnvst diita intrac t ad t t ad v v vdd ad 2c t cs rd cs rd r hih cs ad ad rd cnvst s data s cs rd prvis cnvrsin data n data p d t r (c r para intrac t ad sr par t t crrnt cnvrsin s datas cs rd 2 s p d t r (r c
rev. e e16e ad7664 previous conversion t 1 t 3 t 12 t 13 t 4 cs = 0 cnvst , rd busy databus figure 15. slave parallel data timing for reading (read during convert) serial interface the ad7664 is configured to use the serial interface when the ser/ par hih t ad s sdt t z sc t astr sria intrac i c t ad sc t int t ad snc t sc snc d rdcsdin s cs rd cnvst snc sc sdt 2 2 2 2 2 2 2 2 22 2 d d d2 d d t int rdcsdin invsc invsnc 2 s d t r (r c t int rdcsdin invsc invsnc 2 2 2 2 2 2 2 22 d d d2 d d 2 s cs rd cnvst snc sc sdt s d t r (r p c c
rev. e ad7664 e17e b ecause the ad7664 is used with a fast throughput, the mas- ter read during conversion mode is the most often recom- mended serial mode, when it can be used. in this mode, the serial clock and data toggle at appropriate instants that mini- mize potential feedthrough between digital activity and the critical conversion decisions. in read-after-conversion mode, it should be noted that, unlike in other modes, the signal busy returns low after the 16 data bits are pulsed out and not at the end of th e con version phase, which results in a longer busy width. slave serial interface external clock the ad7664 is configured to accept an externally supplied serial data clock on the sclk pin when the ext/ int hih i t cs cs rd t a hih 2 ad t ad s s hih d c d r c t s a s cs rd t s a a hz ad rdcsdin t a s cnvst i rdcsdin sc sdt t s s sc cnvst cs sc sdt rdcsdin s s data t ad (dnstra s t cnvst cs sc ad 2 (pstra rdcsdin sdt sc in cs in cnvst in t ad dc c sc sdt d d d d d cs s sdin t int invsc 2 2 rd s s d t r (r c
rev. e e18e ad7664 external clock data read during conversion figure 20 shows the detailed timing diagram of this method. during a conversion, while both cs rd t s t rdrrr hi h t rdcsdin hih t hz i 2 hz n hz i t hz i hz n 2 hz icrprcssr intracin t ad t ad i a ad adc t ad adsp2 spi dsp spi i (adsp2 2 ad spi adsp2 t dsp ad t t t (s dsp t (spi adsp2 (str c p (cp c p (cpha spi i (tid spi (spict t spi adc spis (p adsp2 cnvst ad cs s is sc p ts sdt sc rd invsc t int sr par dvdd additina pins ittd r carit p 2 i ad spi i sdt cs sc d d d d d 2 2 cnvst s t int invsc rd 2 s s d t r (r p c c
rev. e ad7664 e19e application hints bipolar and wider input ranges in some applications, it is desired to use a bipolar or wider ana- log input range like, for instance, 10 v, 5 v, or 0 v to 5 v. although the ad7664 has only one unipolar range, by simple modifications of the input driver circuitry, bipolar and wider input ranges can be used without any performance degradation. figure 22 shows a connection diagram that allows this. com ponent values required and resulting full-scale ranges are shown in table iii. for applications where accurate gain and offset are desired, they can be calibrated by acquiring a ground and a voltage reference using an analog multiplexer, u2, as shown for bipolar input ranges in figure 22. u1 2.5v ref analog input r2 r3 r4 100nf r1 u2 c ref in ingnd ref refgnd 1 f ad7664 5 10nf figure 22. using the ad7664 in 16-bit bipolar and/or wider input ranges table iii. component values and input ranges input range r1 (k ) r2 (k ) r3 ( k ) r4 ( k ) 10 v 1 8 10 8 5 v 1 4 10 6.67 0 v to e5 v 1 2 none 0 layout the ad7664 has very good immunity to noise on the power supplies, as can be seen in figure 9. however, care should still be taken with regard to grounding layout. the printed circuit board that houses the ad7664 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be easily separated. digital and analog ground planes should be joined in only one place, preferably underneath the ad7664, or, at least, as close as possible to the ad7664. if the ad7664 is in a system where multiple devices require analog-to-digital ground connections, the connection should still be made at one point only, a star ground point that should be established as close as possible to the ad7664. it is recommended to avoid running digital lines under the device, because these couple noise onto the die. the analog ground plane should be allowed to run under the ad7664 to avoid noise co upling. fast switching signals like cnvst c t t t ad ad d avdd dvdd vdd a sr adc t dvdd ad avdd vdd dvdd avdd rc vdd dvdd t ad innd rnd and dnd nd innd rnd and adc t dnd nd ad p a ad vaad ad t pc va cntrrd2
rev. e e20e ad7664 48-lead low profile quad flat package [lqfp] (st-48) dimensions shown in millimeters top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc 7.00 bsc sq seating plane 1.60 max 0.75 0.60 0.45 view a 9.00 bsc sq pin 1 0.20 0.09 1.45 1.40 1.35 0.08 max coplanarity view a rotated 90 ccw seating plane 10 6 2 7 3.5 0 0.15 0.05 compliant to jedec standards ms-026bbc 48-lead lead frame chip scale package [lfcsp] 7 x7 mm body (cp-48) dimensions shown in millimeters pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 bottom view 5.25 5.10 4.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 typ 1.00 0.85 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 sq seating plane 0.25 min compliant to jedec standards mo-220-vkkd-2 outline dimensions
rev. e ad7664 e21e revision history location page 1/04?data sheet changed from rev. d to rev. e. changes to title . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 10/03?data sheet changed from rev. c to rev. d. changes to title . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 added pulsar selection table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 added new tpc 2, 3, and 13 and renumbered successive tpcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 changes to circuit information section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 changes to driver amplifier choice section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 replaced microprocessor interfacing section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 deleted figure 22 and renumbered successive figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 changes to table iii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 added cp-48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 11/01?data sheet changed from rev. b to rev. c. edits to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edits to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 edits to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 tpc 12 replaced with new data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 edits to voltage reference input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 edits to outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8/01 revision history continued on next page
rev. e e22e ad7664 revision history location page 8/01?data sheet changed from rev. a to rev. b. edit to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edit to product highlights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edit to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 edit to timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 edit to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 edit to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 edit to pin function descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 edits to tpc 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 edits to tpcs 7, 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 edit to figure 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 edit to driver amplifier choice section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 edit to figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 edit to conversion control section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 edit to voltage reference input section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 edit to external clock section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 edit to figure 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 edit to figure 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 edits to bipolar and wider input range section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 edits to figure 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 edit to table ii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
e23e
e24e c02046e0e1/04(e)

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